DSTINI1: These are SMC91C96 input bits. They can be used as general-purpose I/O bits or hardware handshaking signals.

TStik: These are dual-purpose port pins. These signals can be used as general purpose I/O bits or hardware handshaking signals. Since many people use Serial0 for JavaKit loader use, Systronix socket boards dedicate the TINI400 hardware handshake lines to Serial4.

DSTINI1: these are SMC91C96 output bits.

TStik: These are dual-purpose port pins. These signals can be used as general purpose I/O bits or hardware handshaking signals. Since many people use Serial0 for JavaKit loader use, Systronix socket boards dedicate the TINI400 hardware handshake lines to Serial4.

DSTINI1: serial1 uses P5.2 (RX1) and P5.3 (TX1) which can also serve as the second CAN port. These signals can be used as TTL-level serial1 signals. Serial1 can also be used for 1-Wire communication by enabling the DS2480 serial to 1-Wire interface (by asserting the EN2480 signal).

TStik: RX1 and TX1 do not have an alternate CAN1 function, and RX1 and TX1 are not present on the SIMM72 connector. Serial1 is dedicated to 1-Wire. (If you want another serial port, the new Serial4 is available.) The external 1-Wire net appears on Simm72.8, the same as DSTINI1.

DSTINI1 uses this signal to control the function of serial1: as an asynchronous serial port or as a 1-Wire network port.

TStik1 dedicates serial1 to 1-Wire. On TStik2, Serial1 can be used for 1-Wire or as asynchronous serial. TTL-level TX1 and RX1 are available on the same edge contacts as TINI390.

TStik1 and TStik2 do not make TTL level Serial0 signals available. Since Serial0 is typically dedicated to slush, there's little reason to want such access. This is especially true on TStik, which adds a new UART - Serial4.

CAN or I2C
10 - P1.1/SCL/P5.0/CTX
11 - P1.0/SDA/P5.1/CRX

recommended for full time CAN on TStik2

DSTINI1: P5.0 (CTX) and P5.1 (CRX) can be used as CAN signals These also are used by I2C: P5.0 (SCL/clock) and P5.1 (SDA/data). Because these port pins share SIMM72 positions, you cannot use CAN0 and I2C at the same time.

On TStik2, these pins may be used for CAN full time, with I2C on pins 21 and 22. For compatability with older TStiks, CAN and I2C can still be shared on these pins 10 and 11 as they also are on TINI390 and SNAP.

TStik provides a software-driven configuration register to select whether CAN (P5.0 and P5.1) or I2C (P1.0 and P1.1) appears on Simm72 pins 10 and 11. If you are not using these pins as CAN/I2C they are usable as general purpose I/O pins. On TStik, the CAN and I2C signals are unbuffered, but are bidirectional TTL level, 3.3V voltage range, 5V tolerant. Since TStik uses no buffering, you may use external pullups on the SDA line. The SCLK line is bidirectional, so peripherals can pull it low.

18 - SMCRST

P3.4, controlled by TINI firmware, resets ethernet controller and peripherals on socket board.

Buffered DS80C400 RSTOL(L), called PRST

DSTINI1: SMCRST drives the reset input of the SMC91C96 ethernet controller. It is also used on the Dallas E50 to reset the parallel port and DUART. SMCRST is I/O pin P3.4, and is controlled by TINI firmware. SMCRST is driven high for 5 to 10 seconds following any hardware reset (power-on reset, pushbutton reset, or DTR reset from JavaKit). SMCRST is asserted while JavaKit is talking to the TINI bootloader.

TStik: PRST has a similar but not identical implementation. P3.4 is no longer available for use as a firmware reset. PRST is a buffered and inverted version of the DS80C400 RSTOL signal. PRST can also be controlled by the TStik configuration register. For complete details please see the TStik.72.nb Signal Description: PRST

P6.1/CE5

DSTINI1: CE0 must be connected to RCE0 to boot from onboard flash. Alternatively, CE0 can be used to enable external boot memory, and RCE0 is driven high to disable the onboard flash.

TStik boots from internal ROM. There is no equivalent for this signal. TStik uses P6.1/CE5 as the SPI MOSI (Master Out, Slave In) signal and P6.2/CE6 as SPI MISO (MAster In Slave Out). When TINI400 boots up, CE5 is configured as a 2 MByte chip select, so the Systronix TStik and SPI APIs reconfigure it appropriately.

P6.2/CE6

general purpose I/O bits

DSTINI1: these are used as general purpose I/O, peripheral chip selects (1 MByte max), or SPI pins when using the optional Dallas SPI package. (TINI390 offers only one SPI chip select.)

TStik: these are not usable as peripheral chip selects because merging code and data space on CE0 and CE1 prevents such use. For more information on these pins please see the TStik.72.nb Signal Description: PCE

DSTINI1: One potential 'Achilles heel' is the close physical proximity of A18 to the ethernet signal ETH3. The SIMM72 pads are 0.008 inches apart. There is some speculation that a noise spike on the ethernet connection could arc over to A18, mortally wounding the controller and therefore the TINI390 module.

TStik has no external address and data bus and does not bring A18 to the SIMM72 connector, so it cannot have this vulnerability.

67, 68, 69, 70
VCC

The TINI390 chipset uses 5 volts. The TINI400 chipset uses 3.3 and 1.8 volts. Since the TINI390 Simm72 module only has 5 volt supply pins, TStik uses onboard converters to generate 3.3 and 1.8 volts.

TStik voids pins 67 and 70 so that there is virtually no chance of a voltage surge on Ethernet ETH1 (pin 66) arcing to VCC and damaging TStik. Pin 70 is not used on TStik.72.nb, but is reserved for possible future use.

NOTES